This invention relates generally to voltage regulators and more particularly to voltage regulators for integrated circuits requiring low voltage and low power consumption.
FIG. 2 shows an example of a prior art voltage regulator for a clock IC requiring low voltage and low current consumption. The reference voltage is formed by a p-channel insulated gate field-effect transistor (IGFET) 206 whose gate and drain are connected and a constant current source 201. By designing the .beta. of transistor 206 relatively large, the voltage V.sub.DD -V.sub.1, expressed as V.sub.1, becomes nearly equal to the threshold voltage V.sub.T206 +.alpha. of the transistor 206. The output of operational amplifier (OP-AMP) 202 is impressed on the gate of transistor 204. Where the threshold voltage of the n-channel MOS transistor 216 whose gate and drain are connected is V.sub.T216, the voltage V.sub.T216 +.alpha. is output as the potential difference between V.sub.1 and V.sub.2. Source 203 is a constant current source for transistor 216.
Considering the overall operation of the circuit of FIG. 2, the voltage V.sub.DD -(V.sub.T206 +V.sub.T216 +.alpha.") is output to the terminal, V.sub.OUT, and when V.sub.DD is considered as the reference voltage, this output a constant voltage, i.e., the sum of voltages of the threshold voltage of p-channel transistor 206 and the threshold voltage of n-channel transistor 216 becomes the output, V.sub.OUT.
FIG. 3 shows a graph in which the voltage sums of V.sub.T206 +V.sub.T216 and the constant voltage output, V.sub.OUT, of the prior art circuit of FIG. 2 are plotted respectively on the horizontal axis and the vertical axis of the graph. In the figure, (a) shows the case in which the threshold voltage (V.sub.TP below) of the p-channel transistor and the threshold voltage (V.sub.TN below) of the n-channel transistor are both high, (b) shows the case in which V.sub.TP is high and V.sub.TN is low, (c) shows the case in which V.sub.TP is low and V.sub.TN is high, and (d) shows the case in which both V.sub.TP and V.sub.TN are low. These values are idealistically considered to be a straight line condition, as represented by the doted line in FIG. 3. However, actual measured data shows that the threshold voltage (V.sub.TH) of OP-AMP 202 also varies at the same time while the conductance coefficient .beta. of transistor 206 also fluctuates so that they vary from the ideal straight line condition as illustrated in FIG. 3.
When a CMOS oscillation circuit is connected as the load to the output of the circuit of FIG. 2, the oscillation start/stop voltage is proportional to SV.sub.TH, assuming .SIGMA.V.sub.TP +V.sub.TN =.SIGMA.V.sub.TH. Considering that the current consumption is inversely proportional to .SIGMA.V.sub.TH, on an ideal straight line condition, when V.sub.TH rises, for example, the oscillation start/stop voltage rises and the current consumption drops. However, since the power source of the oscillation circuit is being supplied from a voltage regulator, the power source output also rises, and when considered overall, the oscillation start/stop voltage does not rise. Also, if V.sub.TH drops, the oscillation start/stop voltage should drop and the current consumption will rise. However, since the constant voltage also drops, overall, the two values hardly change at all.
That is, a stable oscillation circuit can be supplied with respect to V.sub.TH, but actually the constant voltage output is shifted from the ideal straight line condition, and the nonlinear portion results in a drop in yield.
It is an object of the present invention to provide a constant voltage source proximating an ideal straight line characteristic.